Cornelis Networks, Inc.: Ethernet Host Adaptor ASIC Design Engineer
About Cornelis Networks
Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Their architecture seamlessly integrates hardware, software, and system-level technologies to maximize the efficiency of GPU, CPU, and accelerator-based compute clusters at any scale. They are committed to innovation, performance, and scalability, solving the world’s most demanding computational challenges with their next-generation networking solutions.
They are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, their team spans multiple U.S. states and six countries, and they continue to expand with exceptional talent in onsite, hybrid, and fully remote roles.
Responsibilities
- Develop microarchitecture specifications for packet processor and high-speed pipelined data path designs for host ethernet adaptors emphasizing low-latency performance.
- Implement RTL designs using Verilog/System Verilog for high-speed data paths and packet processing logic.
- Collaborate with verification engineers to create block- and system-level test plans to ensure comprehensive design coverage.
- Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure.
- Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues.
- Contribute to performance optimization and power-aware design strategies for Host Fabric Interface subsystems.
Minimum Qualifications
- B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field.
- 7+ years of post-college experience in digital design with proficiency in Verilog and System Verilog.
- Experience in RTL design for high-speed data paths or packet processing in ASICs.
- Deep understanding of Host Ethernet adaptor architectures.
- Familiarity with timing closure and modern physical design methodologies.
- Proven ability in system-level debug and root cause analysis of technical issues.
- Strong verbal and written communication skills.
Preferred Qualifications
- Knowledge of Ethernet architecture and networking protocols.
- Prior experience with RTL development for Ethernet host adapters and system debug.
- Expertise in multiple clock domain designs and asynchronous interfaces.
- 7+ years of experience with scripting languages such as TCL, Python, or Perl.
- Familiarity with EDA tools like Design Compiler, Spyglass, or PrimeTime.
Location
This is a remote position for employees residing within the United States.
Compensation and Benefits
They offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits.
Your base salary will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives.
In addition to your base pay, you’ll have access to a broad range of benefits, including:
- Medical, dental, and vision coverage
- Disability and life insurance
- Dependent care flexible spending account
- Accidental injury insurance
- Pet insurance
- Generous paid holidays
- 401(k) with company match
- Open Time Off (OTO) for regular full-time exempt employees
- Sick time, bonding leave, and pregnancy disability leave